Asynchronous digital data capture is currently done by using specific load board hardware or special hardware within a test system. The data is clocked in first in first out (FIFO) by a Device Under Test (DUT). Then, the data is clocked out of the FIFO into the test system by a clock synchronous with the test system.
Unfortunately, the specific load board hardware adds design cost, design time, and maintenance. In addition, this extends the time to market for a solution.